In practice, the development of an ASIC (Application-Specific Integrated Circuit) circuit stretches over a duration of the order of several months, which is relatively long in relation to the development cycle of modern electronic devices.
To test the functionality of a device such as a smartphone, parallel to the development of each ASIC circuit that it must comprise, a prototype of each ASIC circuit is produced in the form of a system with FPGA components.
An FPGA (Field-Programmable Gate Array) component is a programmable logic array able to be reprogrammed after its manufacture.
On account of the large, and growing, computational power of the ASIC circuits having to be prototyped, it is necessary to use not one FPGA component, but a plurality of FPGA components interconnected by an electronic board bearing them so as to implement the logic design in the FPGA system.
To develop a multi-FPGA prototype, the logic design, i.e. the functional behavior to be implemented, takes the form of a list of logical interconnections (commonly known as a design netlist), the definition of the board taking the form of a list of interconnections between FPGA components (commonly known as a board netlist), which defines each FPGA and the connections between these FPGAs.
Such a system thus comprises, on the one hand, flip-flops, i.e. FPGA sequential cells; it is possible to consider a flip-flop as a starting or end point of a synchronization path, depending on whether the synchronization path in question starts at this cell or ends at this cell.
It also comprises, on the other hand, assemblies of FPGA logic cells that communicate with each other using signals, these logic cells being considered bystanders in the synchronization path. A logic cell may thus be neither a starting point nor an end point, but be characterized by the delay that it introduces in the synchronization path of which it is a part.
Timing analysis is the calculation of the expected synchronization: the travel time of the longest synchronization path between a starting-point flip-flop and an end-point flip-flop allows the system clock frequency at which the board will be able to operate to be determined.
Currently, solely an FPGA timing analysis, called an “intra-FPGA timing analysis”, is automatically carried out, this making it possible to determine the maximum permissible clock frequency for each FPGA analyzed.
In practice, a frequency analysis based on a complete model of the entirety of the multi-FPGA board, representing all of the logic cells of the system, is impossible, as it would require a colossal computational power and memory capacity, on account of the very large area that modern multi-FPGA boards can have.